datasheet r03ds0020ej0300 rev.3.00 jul 25, 2013 page 1 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 8 - bit 12ch d/a converter with buffer amplifiers r2a20169np/sa/sp application conversion from digital data to analog control data for home - use and industrial equipment. block diagram 20 11 15 16 17 8 gnd clk ld di vcc ao1 18 14 do ao12 13 12 ao2 19 ao11 12 d/a 8 - bit latch 8 - bit upper segment r - 2r d/a converter 8 - bit latch d/a 8 - bit latch d/a 8 - bit latch d/a 8 - bit latch d0 1 2 3 4 5 6 7 8 9 10 11 features 18 17 16 15 14 13 12 11 10 serial data transfer type input can easily be used through a combination of three lines: di, clk, and ld. very small qfn package is added to lineup. it is suitable for a small mounting and reduces the mounting area. description guarantee nonlinearity error : +/ - 1.0lsb, differential nonlinearity error : +/ - 0.7lsb data transfer format: 12 - bit serial data input type by 3 wire ( di, sck, ld ) output buffer op - amps: operable over entire voltage range from almost ground to vcc ( 0 to 5v ) high output current capacity: +/ - 1ma or higher very small size package line - up: qfn - 20 (pin pitch: 0.5mm), tssop - 20 (pin pitch 0.65mm) number for tssop/sop package number for qfn package power on reset 12 - bit shift register d/a 8 - bit latch 8 - bit upper segment r - 2r d/a converter 8 - bit latch d/a 8 - bit latch d/a 8 - bit latch d/a 8 - bit latch d/a 8 - bit latch d/a 8 - bit latch 9 3 2 ao4 ao3 1 v refl 4 ao5 5 ao6 6 ao7 7 ao8 8 v refu 9 10 ao9 ao10 19 20 1 2 3 4 5 6 7 8 outputs incorporate buffer op - amps that have a drive capacity of 1 ma or above for both sink source, and can operate over the entire voltage range from almost ground to vcc ( 0 to 5v ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. the r2a20169 is an integrated circuit semiconductor of cmos structure with 12 channels of built in d/a unnecessary and enabling configuration of a system with few component parts. channel decoder
datasheet r2a20169np/sa/sp page 2 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 pin description pin arrangement pin no. pin name function [qfn] [tssop /sop] 15 17 di serial data input terminal. (input serial data with a 12 - bit data length.) 12 14 do serial data output terminal (data is sequentially output from the msb bit.) 14 16 clk serial clock input terminal (input signal from di terminal is input to 12 - bit shift register at rise of serial clock.) 13 15 ld load terminal (when high level is input to ld terminal, value in 12 - bit shift register is loaded into decoder and 8 - bit latch.) 16 18 ao1 8 - bit resolution d/a converter output terminals (after power - on, all channels are reset and dac data 00h is output.) 17 19 ao2 20 2 ao3 1 3 ao4 2 4 ao5 3 5 ao6 4 6 ao7 5 7 ao8 6 8 ao9 7 9 ao10 10 12 ao11 11 13 ao12 9 11 vcc power supply terminal 18 20 gnd gnd terminal 8 10 v refu d/a converter upper reference voltage input terminal 19 1 v refl d/a converter lower reference voltage input terminal outline: prsp0020dd - b[sp] ptsp0020jb - a [sa] r2a20169sp/sa ao3 ao4 gnd ao2 ao1 di ao5 ao6 ao7 ao8 clk ld do ao12 8 1 7 6 5 4 3 2 20 14 15 16 17 18 19 15 14 13 12 1 2 3 4 r2a20169np (top view) ao4 ao5 clk ld vcc outline: pwqn0020kb - a [np] ao6 ao7 ao9 di gnd r2a20169sp/sa (top view) 6 7 8 20 19 18 r2a20169np v refl v refl v refu v refu ao10 10 9 11 12 13 ao11 vcc ao9 ao2 17 5 ao8 ao11 9 11 ao12 10 ao1 16 do ao3 ao10
datasheet r2a20169np/sa/sp page 3 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 absolute maximum ratings item symbol conditions ratings unit supply voltage vcc - 0.3 to +6.5 v d/a converter upper reference voltage v refu - 0.3 to +6.5 v d/a converter lower reference voltage v refl - 0.3 to +6.5 v buffer amplifier output current i ao continuous - 2.0 to +2.0 ma input voltage vin - 0.3 to vcc+0.3 <+6.5 v output voltage vo - 0.3 to vcc+0.3 <+6.5 v power dissipation pd ta= +85deg 290(np) / 150(sa) / 300(sp) mw thermal derating factor k theta ta> +25deg 7.25(np) / 3.75(sa) / 7.5(sp) mw/deg operating temperature topr - 30 to +85 deg storage temperature tstg - 40 to +125 deg electrical characteristics item symbol test conditions limits unit min typ max supply voltage vcc 2.7 5.0 5.5 v supply current icc clk = 1mhz, vcc =5v, i ao =0a - 0.6 1.8 ma input leak current i ilk v in = 0 to vcc -10 - 10 a input low voltage v il - - 0.2vcc v input high voltage v ih 4.0v < vcc 0.5vcc - - v vcc < 4.0v 0.8vcc - - v output low voltage v ol 4.0v < vcc, i ol =2.0 ma - - 0.4 v vcc < 4.0v, i ol =1.5 ma - - 0.4 v output high voltage v oh i oh = - 400 a vcc ? 0.4 - - v supply voltage rise time *1 t r vcc vcc = 0 ? 2.7v 100 - - s internal reset operating voltage *1 vcc por vcc = 0 ? 2.7v - 1.5 1.9 v power supply restart interval (power supply off on) *1 t por vcc < 0.1v 1 - - ms *1 : when power supply is turned on, internal circuit is initialized by power on reset circuit. but, if re - powered on quickly, initialize is not operate. so, keep the time period of re - powered on (t por ). vcc internal reset signal t por tr vcc < 0.1v (equivalent to tr vcc ) vcc por resetting period gnd gnd resetting period ? digital part ? ( vcc, v refu = +5v +/ - 10%, vcc>v refu , gnd,v refl =0v, ta= - 30 to +85deg, unless otherwise noted ) (ta= +25deg unless otherwise noted)
datasheet r2a20169np/sa/sp page 4 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 ? analog part ? ( vcc,v refu = +5v +/ - 10%, vcc>v refu , gnd,v refl =0v, ta= - 30 to +85deg, unless otherwise noted ) item symbol test conditions limits unit min typ max current dissipation i refu v refu =5v, v refl =0v, i ao =0a, data condition: at maximum current - 1.5 3.0 ma d/a converter upper reference voltage range *2 v refu vcc 3 4.5v 3.5 - vcc v vcc < 4.5v 0.7vcc - vcc d/a converter lower reference voltage range *2 v refl vcc 3 4.5v gnd - vcc - 3.5 v vcc < 4.5v gnd - 0.3vcc buffer amplifier output voltage range v ao i ao = +/ - 100 a 0.1 - vcc ? 0.1 v i ao = +/ - 500 a 0.2 - vcc ? 0.2 v buffer amplifier output drive range i ao upper side saturation voltage = 0.3v, lower side saturation voltage = 0.2v - 1.0 - 1.0 ma differential nonlinearity s dl v refu = 4.79v, v refl = 0.95v, vcc = 5.5v (15mv/lsb), without load (i ao =0a) - 0.7 - 0.7 lsb nonlinearity s l - 1.0 - 1.0 lsb zero code error s zero - 2.0 - 2.0 lsb full scale error s full - 2.0 - 2.0 lsb output capacitive load co - - 0.1 f buffer amplifier output impedance ro - 5.0 - ohm *2 : the output does not necessary be the value with the reference voltage setting range. the output value is determined by the buffer amplifier output voltage range (v ao ).
datasheet r2a20169np/sa/sp page 5 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 item symbol test conditions limits unit min typ max clock frequency f clk - 1.0 10 mhz clock low pulse width t ckl 40 - - ns clock high pulse width t ckh 40 - - ns clock rise time t cr - - 200 ns clock fall time t cf - - 200 ns data setup time t dch 4 - - ns data hold time t chd 30 - - ns ld setup time t chl 40 - - ns ld hold time t ldc 40 - - ns ld high pulse width t ldh 40 - - ns data output delay time t do c l < 100 pf -10 - 50 ns d/a output settling time t ldd ta=25deg, c l <100pf, v ao : 0.5 ?? 4.5v, the time until the output becomes the final value of 1/2 lsb. - - 150 s ac characteristics timing chart clk t cr t cf t ckh t ckl t dch t chd t chl t ldh t ldc t ldd di ld d/a output t do do output ( vcc, v refu = +5v +/ - 10%, vcc >v refu , gnd=v refl = 0v, ta = - 30 to +85deg, unless otherwise noted ) (note) timing chart above is a schematic representation of the timing of each signal type. clk signal input is high or low regardless, ld signal high input is enabled.
datasheet r2a20169np/sa/sp page 6 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 digital data format last lsb d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0 d1 d2 d3 d4 d5 d6 d7 d/a output 0 0 0 0 0 0 0 0 (v refu ? v refl ) / 256 x 1 + v refl 1 0 0 0 0 0 0 0 (v refu ? v refl ) / 256 x 2 + v refl 0 1 0 0 0 0 0 0 (v refu ? v refl ) / 256 x 3 + v refl 1 1 0 0 0 0 0 0 (v refu ? v refl ) / 256 x 4 + v refl : : : : : : : : : 0 1 1 1 1 1 1 1 (v refu ? v refl ) / 256 x 255 + v refl 1 1 1 1 1 1 1 1 v refu first msb dac data channel select data channel select data d8 d9 d10 d11 chanel selection 0 0 0 0 don?t care 0 0 0 1 ao1 select 0 0 1 0 ao2 select 0 0 1 1 ao3 select 0 1 0 0 ao4 select 0 1 0 1 ao5 select 0 1 1 0 ao6 select 0 1 1 1 ao7 select 1 0 0 0 ao8 select 1 0 0 1 ao9 select 1 0 1 0 ao10 select 1 0 1 1 ao11 select 1 1 0 0 ao12 select 1 1 0 1 don?t care 1 1 1 0 don?t care 1 1 1 1 don?t care dac data
datasheet r2a20169np/sa/sp page 7 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 data timing chart ( model ) di ld d/a output d2 d9 d10 d11 clk d8 d7 d1 d0 msb lsb whether clk input is ?h? or ?l?, high level input of ld signal is recognized. precaution for use analog voltage output 10f + ao1 ao2 ld clk di gnd vcc v refl v refu 10f + 10f + ao11 ao12 standard application circuit mcu there are three terminals (vcc, v refu , v refl ) that should be impressed a constant voltage. when ripple or spike noise is input to this terminal, there is fear that the accuracy of d/a conversion becomes lower and this ic malfunction. so, when use this ic, please connect capacitor between these terminals (vcc, v refu , v refl ) and gnd for stable d/a conversion. this ic?s output amplifier has an advantage to capacitive load, so, it?s no problem at device action when connect capacitor ( 0.1f max ) among output to gnd for every noise elimination.
datasheet r2a20169np/sa/sp page 8 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 prsp0020dd - b [sp] pwqn0020kb - a [np] package dimensions
datasheet r2a20169np/sa/sp page 9 of 9 r03ds0020ej0300 rev.3.00 jul 25, 2013 ptsp0020jb - a [sa] ordering information order part no. package name package code package type no. packing/quantity r2a20169sp#w5 sop - 20 prsp0020dd - b sp embossed taping/2,000 pcs. r2a20169sa#w5 tssop - 20 rtsp0020jb - a sa embossed taping/2,000 pcs. r2a20169np#w5 qfn - 20 pwqn0020kb - a np embossed taping/2,500 pcs.
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